Alternatives and similar repositories for risc-666:

Users that are interested in risc-666 are comparing it to the libraries listed below

• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated 2 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 6 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆49Updated 6 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• swetland / gateware
  A collection of little open source FPGA hobby projects
  ☆48Updated 5 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 5 years ago
• cpantel / DVGHV
  Designing Video Game Hardware in Verilog
  ☆26Updated 5 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆99Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆42Updated 2 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆45Updated last year
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆82Updated 6 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆50Updated 4 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆16Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 3 weeks ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• shacron / sled
  Sled System Emulator
  ☆28Updated this week
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆27Updated 3 years ago
• fontamsoc / pu32
  ☆15Updated last year
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆107Updated 2 years ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated last year
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆16Updated 5 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆23Updated last year
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆60Updated 2 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆104Updated 10 years ago
• franzflasch / linux_for_riscv_em
  Scripts to automate building linux images for my emulator riscv_em
  ☆15Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 9 months ago