lcq2 / risc-666
RISC-V user-mode emulator that runs DooM
☆50Updated 5 years ago
Alternatives and similar repositories for risc-666:
Users that are interested in risc-666 are comparing it to the libraries listed below
- RISC-V Instruction Set Metadata☆41Updated 6 years ago
- RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC☆98Updated 2 years ago
- Exploring gate level simulation☆56Updated 2 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated last year
- J-Core J2/J32 5 stage pipeline CPU core☆51Updated 4 years ago
- Moxie-compatible core repository☆46Updated last year
- This is a higan/Verilator co-simulation example/framework☆49Updated 6 years ago
- Sled System Emulator☆28Updated last month
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆43Updated 2 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- ☆32Updated 4 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- MRSIC32 ISA documentation and development☆90Updated last year
- Enigma in FPGA☆29Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 2 months ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 3 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 3 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆27Updated 3 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- TinyGPUs, making graphics hardware for 1990s games☆107Updated 2 weeks ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- A collection of little open source FPGA hobby projects☆48Updated 5 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆54Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 5 months ago
- A simple GPU on a TinyFPGA BX☆82Updated 6 years ago