Alternatives and similar repositories for risc-666

Users that are interested in risc-666 are comparing it to the libraries listed below

• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 6 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• shacron / sled
  Sled System Emulator
  ☆28Updated this week
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆54Updated 4 years ago
• srokicki / HybridDBT
  ☆33Updated 5 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• jowinter / dmacu
  Minimal CPU Emulator Powered by the ARM PL080 DMA Controller
  ☆36Updated last year
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated 2 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• swetland / gateware
  A collection of little open source FPGA hobby projects
  ☆50Updated 5 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆31Updated 4 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• danielkasza / 9444
  9444 RISC-V 64IMA CPU and related tools and peripherals.
  ☆28Updated 4 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• cr88192 / bgbtech_btsr1arch
  BtSR1 and BJX2 ISA / CPU Architecture
  ☆28Updated last week
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 3 years ago
• franzflasch / linux_for_riscv_em
  Scripts to automate building linux images for my emulator riscv_em
  ☆15Updated last year
• ToNi3141 / RasterIX
  OpenGL 1.x implementation for FPGAs
  ☆100Updated this week
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 4 months ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆44Updated 2 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 6 months ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆57Updated 2 years ago
• sylefeb / tinygpus
  TinyGPUs, making graphics hardware for 1990s games
  ☆151Updated 2 weeks ago