Alternatives and similar repositories for risc-666

Users that are interested in risc-666 are comparing it to the libraries listed below

• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 4 months ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆99Updated 3 years ago
• swetland / gateware
  A collection of little open source FPGA hobby projects
  ☆50Updated 5 years ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆55Updated 2 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 6 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆81Updated 6 years ago
• shacron / sled
  Sled System Emulator
  ☆28Updated 4 months ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆47Updated 3 weeks ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• srokicki / HybridDBT
  ☆33Updated 5 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated 2 years ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆110Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 7 months ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆32Updated 8 years ago
• jowinter / dmacu
  Minimal CPU Emulator Powered by the ARM PL080 DMA Controller
  ☆36Updated last year
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆34Updated 10 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆94Updated 3 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• cr88192 / bgbtech_btsr1arch
  BtSR1 and BJX2 ISA / CPU Architecture
  ☆27Updated 3 weeks ago