lambdaconcept / mfcc
A Mel-frequency cepstrum core in FPGA
☆19Updated 3 years ago
Alternatives and similar repositories for mfcc
Users that are interested in mfcc are comparing it to the libraries listed below
Sorting:
- Voice Activity Detector based on MFCC features and DNN model☆19Updated last year
- ☆13Updated 4 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated last week
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆44Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Updated 4 years ago
- Python script for controlling the debug-jtag port of riscv cores☆14Updated 4 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆28Updated 6 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- ULPI Link Wrapper (USB Phy Interface)☆26Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Neural Engine, 16 input channels☆13Updated 2 years ago
- ☆19Updated last year
- Delta Sigma DAC FPGA☆37Updated 2 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆33Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- iDEA FPGA Soft Processor☆16Updated 8 years ago