A Mel-frequency cepstrum core in FPGA
☆21Jun 30, 2021Updated 5 years ago
Alternatives and similar repositories for mfcc
Users that are interested in mfcc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 7 years ago
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆17Dec 27, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Aug 3, 2026Updated last week
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 7 years ago
- VGA Tutorial for DE1☆16Apr 21, 2015Updated 11 years ago
- deep learning and scientific computing framework with native CPU and GPU backend for the Scala programming language☆33Apr 22, 2025Updated last year
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆17Mar 3, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated last year
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13May 21, 2017Updated 9 years ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Updated this week
- 一个基于 TradingAgents 多智能体量化分析框架的现代化 Web 版本，同时支持美股、港股和A股☆14Updated this week
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆19Jul 25, 2023Updated 3 years ago
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 5 years ago
- SpinalHDL code to drive a 64*64 pixel HUB75E module with an ICE40☆33May 9, 2020Updated 6 years ago
- ☆14Oct 20, 2015Updated 10 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆70Dec 18, 2024Updated last year
- Cheapest UAC2 using STM32F407+USB3300☆22Feb 26, 2025Updated last year
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Teacher - student distillation using DeepSpeed☆20Oct 7, 2022Updated 3 years ago
- ☆12May 20, 2021Updated 5 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- ☆15Nov 26, 2024Updated last year
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated last year
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆81Jun 1, 2021Updated 5 years ago
- ☆11Dec 18, 2017Updated 8 years ago