A Mel-frequency cepstrum core in FPGA
☆21Jun 30, 2021Updated 5 years ago
Alternatives and similar repositories for mfcc
Users that are interested in mfcc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Voice Activity Detector based on MFCC features and DNN model☆32Jul 3, 2023Updated 3 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆17Dec 27, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Updated this week
- Super Audio CD ISO-Image decoder addon☆19Aug 23, 2026Updated last month
- deep learning and scientific computing framework with native CPU and GPU backend for the Scala programming language☆33Apr 22, 2025Updated last year
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- USB2.0 Device Controller IP Core☆20Aug 18, 2023Updated 3 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13May 21, 2017Updated 9 years ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- ☆10Feb 13, 2025Updated last year
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Aug 21, 2026Updated last month
- fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard☆17Aug 3, 2019Updated 7 years ago
- 一个基于 TradingAgents 多智能体量化分析框架的现代化 Web 版本，同时支持美股、港股和A股☆14Sep 11, 2026Updated last week
- The NandBug Software☆13May 23, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆13Jun 14, 2020Updated 6 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 6 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 5 years ago
- SpinalHDL code to drive a 64*64 pixel HUB75E module with an ICE40☆33May 9, 2020Updated 6 years ago
- ☆12Oct 20, 2015Updated 10 years ago
- Experiments with Yosys cxxrtl backend☆49Jan 16, 2025Updated last year
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆70Dec 18, 2024Updated last year
- Cheapest UAC2 using STM32F407+USB3300☆22Feb 26, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- Teacher - student distillation using DeepSpeed☆20Oct 7, 2022Updated 3 years ago
- ☆12May 20, 2021Updated 5 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated 2 years ago
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆81Jun 1, 2021Updated 5 years ago