Alternatives and similar repositories for hw-ci

Users that are interested in hw-ci are comparing it to the libraries listed below

• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆38Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 3 weeks ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated last month
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆62Updated last month
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆48Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 2 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 5 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆58Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆72Updated this week
• wallento / cocotbext-wishbone
  ☆14Updated 8 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆69Updated last year
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆29Updated 7 months ago
• schang412 / cocotbext-spi
  ☆23Updated 4 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆11Updated 5 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 6 months ago