Alternatives and similar repositories for TMR

Users that are interested in TMR are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆17Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆60Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆28Updated 4 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• lnls-dig / general-cores
  general-cores
  ☆19Updated 8 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆12Updated last month
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆58Updated last week
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆22Updated 3 months ago
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆15Updated 9 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆24Updated 3 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago