Alternatives and similar repositories for docker

Users that are interested in docker are comparing it to the libraries listed below

• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆47Updated this week
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆51Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆119Updated last year
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆58Updated 9 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆82Updated last month
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last week
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 5 years ago
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆16Updated 9 months ago
• VHDL / news
  VHDL related news.
  ☆27Updated this week
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆52Updated 3 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• pieter3d / simview
  ☆91Updated 3 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆73Updated 4 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆100Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• nobodywasishere / vhdlref
  A usable language reference for VHDL that is concise, direct, and easy to understand.
  ☆26Updated 4 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆64Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month