FSillT / QCADesigner-E

Related projects: ⓘ

• msoeken / cirkit
  A circuit toolkit
  ☆95Updated 4 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆176Updated 5 months ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆35Updated 2 months ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated last year
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆48Updated 2 weeks ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆27Updated last month
• pkuzjx / eda-collection
  ☆95Updated 4 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆45Updated last year
• msoeken / kitty
  C++ truth table library
  ☆49Updated 5 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆53Updated 3 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last year
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆67Updated last year
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆159Updated 3 weeks ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆93Updated 2 weeks ago
• lsils / mockturtle
  C++ logic network library
  ☆204Updated this week
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆45Updated 2 months ago
• lsils / bill
  C++ header-only reasoning library
  ☆11Updated 2 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆22Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆53Updated 4 years ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆44Updated last week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆29Updated last month
• IntelLabs / FloorSet
  ☆46Updated last month
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆105Updated last month
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆59Updated this week
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆72Updated this week
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆79Updated 2 years ago
• idea-fasoc / fasoc
  ☆52Updated 11 months ago
• nbulsi / also
  A logic synthesis tool
  ☆64Updated last year
• cda-tum / fiction
  An open-source design automation framework for Field-coupled Nanotechnologies
  ☆56Updated this week