Serialize & deserialize device tree binary using serde
☆23Dec 4, 2025Updated 3 months ago
Alternatives and similar repositories for serde-device-tree
Users that are interested in serde-device-tree are comparing it to the libraries listed below
Sorting:
- 遍历设备树二进制对象☆14Nov 22, 2025Updated 4 months ago
- Coffer is a RISC-V trusted execution environment developed in Rust.☆20Mar 3, 2022Updated 4 years ago
- RustSBI bootloader firmware and debug suite for Allwinner D1 SoC boards, including Nezha, Lichee and more☆19Oct 9, 2024Updated last year
- Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension☆16Oct 21, 2024Updated last year
- A compiler for higher rank ML with type classes☆13Aug 29, 2020Updated 5 years ago
- hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.☆49Feb 20, 2023Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Test run any program on D1 Nezha board flash☆27Jul 29, 2022Updated 3 years ago
- Game Engine From Scratch -- Rust China Conference 2020 topic by LemonHX and his team.☆14Dec 16, 2020Updated 5 years ago
- 自嗨虚拟化软件 - 'Enjoy yourself' type-1 hypervisor software☆25Apr 21, 2022Updated 3 years ago
- Rust Hardware Abstraction Layer for Bouffalo chips☆23Sep 27, 2025Updated 5 months ago
- ☆20Mar 1, 2026Updated 3 weeks ago
- 🎉My Collections of CUDA Kernels~☆10Jun 25, 2024Updated last year
- 没分支的 rCore-Tutorial☆51Jan 8, 2026Updated 2 months ago
- RISC-V V Extension Encoder☆11Jul 28, 2022Updated 3 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆42Aug 15, 2025Updated 7 months ago
- ☆15Mar 15, 2026Updated last week
- Low level access to T-Head Xuantie RISC-V processors☆34Feb 17, 2026Updated last month
- An EFI application to play Bad Apple☆10Dec 28, 2021Updated 4 years ago
- A tool to flash BL602 via JTAG + serial without pressing buttons / setting jumpers☆12Jun 3, 2022Updated 3 years ago
- QEMU platform SBI support implementation, using RustSBI☆151Sep 26, 2025Updated 5 months ago
- [WIP] A tiny RISC-V hypervisor software written in Rust☆27Dec 8, 2020Updated 5 years ago
- An implementation of ext2 filesystem in Rust☆15Oct 8, 2021Updated 4 years ago
- All public report slides, articles and meeting minutes related to RustSBI☆29Dec 14, 2025Updated 3 months ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- 项目的主仓库☆26Sep 11, 2022Updated 3 years ago
- 实验：rust 实现 llama2 推理☆17Feb 23, 2024Updated 2 years ago
- Julia implementation for Python Restrain JIT☆22Mar 3, 2021Updated 5 years ago
- TileGraph is an experimental DNN compiler that utilizes static code generation and kernel fusion techniques.☆11Sep 18, 2024Updated last year
- 洛佳的异步内核实验室☆25May 22, 2021Updated 4 years ago
- ☆13Jul 26, 2021Updated 4 years ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆59Nov 30, 2023Updated 2 years ago
- Features like `async-trait`, avoid using `Box` and `dyn`.☆83Sep 2, 2021Updated 4 years ago
- 在 Telegram 上快速模仿迟先生卖弱。☆16Updated this week
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Jul 20, 2023Updated 2 years ago
- TiledKernel is a code generation library based on macro kernels and memory hierarchy graph data structure.☆19May 12, 2024Updated last year
- Building an embedded Rust application on top of the ASF4 C vendor library☆14Mar 16, 2020Updated 6 years ago
- a coroutinue lib writen by pure C☆10Feb 24, 2021Updated 5 years ago