CSL-KU / IsolBenchLinks
A set of synthetic benchmarks used in IEEE RTAS 2016 paper by Prathap et al.,
☆17Updated this week
Alternatives and similar repositories for IsolBench
Users that are interested in IsolBench are comparing it to the libraries listed below
Sorting:
- DRAM Bank-Aware Kernel Memory Allocator☆44Updated 2 weeks ago
- TACLe Benchmarks☆50Updated 11 months ago
- Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-core Processors☆55Updated 2 weeks ago
- a Pin tool for collecting microarchitecture-independent workload characteristics☆60Updated last year
- Collection of synchronization micro-benchmarks and traces from infrastructure applications☆47Updated 2 months ago
- Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors☆41Updated 6 years ago
- Machine-readable data describing Arm architecture and implementations. Includes JSON descriptions of implemented PMU events.☆55Updated 8 months ago
- ☆20Updated 5 years ago
- Memory System Microbenchmarks☆63Updated 2 years ago
- Repeated access to L2-containable loops to look for snoop filter conflicts on Intel Skylake Xeon processors.☆29Updated 7 years ago
- A false sharing detection and repair tool☆14Updated 6 years ago
- PTLsim and QEMU based Computer Architecture Research Simulator☆130Updated 3 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- The Splash-3 benchmark suite☆44Updated 2 years ago
- A survey on architectural simulators focused on CPU caches.☆16Updated 5 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- CleanupSpec (MICRO-2019)☆16Updated 4 years ago
- Virtualisation platform using CHERI for isolation and sharing☆39Updated last year
- Stable, non-KVM version of PTLsim.☆29Updated 9 years ago
- HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs☆30Updated last year
- Interprocedural Basic Block Code Layout Optimization☆18Updated 6 years ago
- The implementation of HawkEye, our research system: "HawkEye: Efficient Fine-grained OS Support for Huge Pages" from ASPLOS 2019.☆20Updated 4 years ago
- A suite of simple programs to test Intels' TSX extension☆14Updated 8 years ago
- PARSEC Benchmark http://parsec.cs.princeton.edu 3.0-beta-20150206 ported to Ubuntu 22.04 and with proper version control and SPLASH2 port…☆98Updated 10 months ago
- Tools and experiments for 0sim. Simulate system software behavior on machines with terabytes of main memory from your desktop.☆21Updated 5 years ago
- Tools to track memory accesses in applications and visualize the patterns to reveal opportunities for optimization.☆92Updated 10 years ago
- The MiBench testsuite, extended for use in general embedded environments☆106Updated 12 years ago
- A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)☆23Updated 7 years ago
- An unofficial mirror of the core PARSEC 3.0 benchmark suite with patches to run on x86_64 Arch Linux and generalize builds.☆120Updated 3 years ago