Alternatives and similar repositories for specs-markdown

Users that are interested in specs-markdown are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆79Updated 6 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆53Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆54Updated 4 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆27Updated 6 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last week
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• larkmjc / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆127Updated 2 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆39Updated 10 years ago
• hex-five / multizone-fpga
  This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…
  ☆32Updated last year
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆25Updated 6 years ago
• riscv / riscv-test-env
  ☆51Updated last week
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆86Updated 2 years ago
• riscvarchive / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 8 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 7 months ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago