Alternatives and similar repositories for specs-markdown

Users that are interested in specs-markdown are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆106Updated 4 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆78Updated 6 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆27Updated 6 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆128Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated last month
• riscvarchive / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• riscv-mcu / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC. Tweaked for microcontrollers.
  ☆33Updated last month
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated last year
• riscv / riscv-test-env
  ☆51Updated 2 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆48Updated 3 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆165Updated 5 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• PulseRain / Rattlesnake
  PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
  ☆34Updated 6 years ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆54Updated 4 years ago