Alternatives and similar repositories for specs-markdown:

Users that are interested in specs-markdown are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆26Updated 5 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆89Updated 5 months ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 4 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆75Updated 5 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 4 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 2 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆38Updated 7 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• riscv / riscv-test-env
  ☆45Updated 2 months ago
• bonfireprocessor / bonfire-cpu
  FPGA optimized RISC-V (RV32IM) implemenation
  ☆34Updated 4 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 2 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 7 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago