emb-riscv / specs-markdownLinks
The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
☆28Updated 3 years ago
Alternatives and similar repositories for specs-markdown
Users that are interested in specs-markdown are comparing it to the libraries listed below
Sorting:
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆31Updated 10 months ago
- RISC-V Configuration Structure☆41Updated 9 months ago
- ☆64Updated 6 years ago
- A port of FreeRTOS for the RISC-V ISA☆77Updated 6 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Naive Educational RISC V processor☆87Updated last month
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- ☆50Updated 3 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Simple machine mode program to probe RISC-V control and status registers☆123Updated 2 years ago
- FreeRTOS for RISC-V☆26Updated 6 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆28Updated 7 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Updated 2 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…☆86Updated last year
- ☆62Updated 4 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year