Alternatives and similar repositories for coffer

Users that are interested in coffer are comparing it to the libraries listed below

• OS-F-4 / usr-intr
  项目的主仓库
  ☆25Updated 2 years ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆119Updated last month
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• Gallium70 / rv-n-ext-impl
  ☆13Updated 2 years ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• rustsbi / slides
  All public report slides, articles and meeting minutes related to RustSBI
  ☆29Updated 3 weeks ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆56Updated last year
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆58Updated 2 months ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆48Updated 2 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆20Updated 3 weeks ago
• stemnic / rustyvisor
  Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension
  ☆16Updated 9 months ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated 2 years ago
• YdrMaster / dtb-walker
  遍历设备树二进制对象
  ☆12Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆58Updated last week
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 3 years ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆40Updated 5 months ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• riscv / virtual-memory
  ☆38Updated 3 years ago
• oscomp / proj47-tee-os
  面向可信执行环境的OS。
  ☆12Updated 2 months ago
• rcore-os / RVM
  Rcore Virtual Machine
  ☆116Updated last year
• rustsbi / sbi-rt
  Simple RISC-V SBI runtime library; designated for supervisor use
  ☆24Updated last year
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆106Updated 8 months ago
• rustsbi / plic
  Rust support for RISC-V Platform-Level Interrupt Controller
  ☆10Updated 2 years ago
• oscomp / proj6-user-level-interrupt
  基于FPGA实现用户态中断硬件机制与优化操作系统内核
  ☆9Updated 4 months ago