inneralien / Tizzy

Related projects ⓘ

Alternatives and complementary repositories for Tizzy

• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆26Updated 6 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated this week
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆19Updated last week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆46Updated this week
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated this week
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆47Updated 9 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆62Updated 4 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• aolofsson / POSH
  ☆39Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆47Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 weeks ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆23Updated this week
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆52Updated 7 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆63Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago