Alternatives and similar repositories for Information

Users that are interested in Information are comparing it to the libraries listed below

• rivosinc / JumpStart
  Framework for writing tests for RISC-V CPU/SOC validation.
  ☆11Updated 3 weeks ago
• five-embeddev / riscv-csr-access
  RISC-V CSR Access Routines
  ☆15Updated 2 years ago
• quic / qbox
  Qbox
  ☆73Updated last week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆157Updated 6 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last week
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆55Updated 11 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆45Updated 4 years ago
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆127Updated last week
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆46Updated 10 months ago
• riscv / riscv-test-env
  ☆51Updated 2 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆29Updated last week
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆51Updated 4 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆87Updated 4 years ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆79Updated last month
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• tenstorrent / cosim-arch-checker
  Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
  ☆21Updated last month
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆73Updated 11 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• pulp-platform / axi_llc
  ☆32Updated 2 weeks ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated last month
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 5 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆15Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago