Alternatives and similar repositories for pulpissimo-zcu102

Users that are interested in pulpissimo-zcu102 are comparing it to the libraries listed below

• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• txstate-pcarch-blue / CPU
  CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
  ☆21Updated 7 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆26Updated 2 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Updated last year
• nicolavianello95 / RISC-V
  Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…
  ☆16Updated 5 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 4 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆73Updated 2 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆33Updated last week
• KireinaHoro / rocket-zynqmp
  ☆13Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆46Updated last year
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 9 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆46Updated 2 years ago
• EECS150 / fpga_labs_sp22
  ☆35Updated 3 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆21Updated 6 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆110Updated 4 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆78Updated last month
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago