Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
☆41Jan 22, 2026Updated 9 months ago
Alternatives and similar repositories for myhdlpeek
Users that are interested in myhdlpeek are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated 2 years ago
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 3 years ago
- MyHDL hardware design language encased in the tasty PygMyHDL wrapper.☆19Jan 22, 2026Updated 9 months ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Jul 7, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 12 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 13 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 14 years ago
- nMigen support for Xilinx Zynq devices☆17Nov 5, 2022Updated 3 years ago
- A Python-based Spice Simulator☆11Jun 17, 2021Updated 5 years ago
- Educational materials and tooling for digital HDL synthesis in Python with myHDL☆36Sep 24, 2018Updated 8 years ago
- ☆19Dec 15, 2023Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Gather and display information on Github repositories that match a given topic.☆17Updated this week
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆18Feb 20, 2020Updated 6 years ago
- Agentic KiCad PCB design workflow for SKiDL — architect, source, code, and verify circuits with AI agents.☆24Apr 8, 2026Updated 6 months ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- ☆18Oct 25, 2021Updated 5 years ago
- Jupyter notebook describing, simulating, and comparing two hardware-based circuits for sorting a list of numbers.☆11Feb 25, 2016Updated 10 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Hi-Speed USB (ULPI) interface Pmod™ module for FPGA boards☆10Jan 27, 2017Updated 9 years ago
- GUI utility for searching and selecting parts and footprints for use with SKiDL.☆12Nov 2, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An FPGA/PCI Device Reference Platform☆32Dec 10, 2020Updated 5 years ago
- A 6800 CPU written in nMigen☆49Jun 16, 2021Updated 5 years ago
- Working space for free software licenses for hardware description language (e.g. VHDL, Verilog, Bluespec) projects☆15Aug 11, 2011Updated 15 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆87Dec 23, 2018Updated 7 years ago
- Inject/eject JSON data to/from KiCad files.☆14Apr 13, 2026Updated 6 months ago
- USB2 core for LiteX☆12Sep 30, 2026Updated last month
- A Pistorm CPU board replacement☆21Dec 7, 2024Updated last year
- ☆64Jul 21, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Library of componentes for PySpice☆13Oct 15, 2019Updated 7 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆23Sep 2, 2023Updated 3 years ago
- Sechzig Compute Module☆11Sep 27, 2026Updated last month
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Eric's branch of Doxverilog (doxygen + doxverilog patch)☆15Jun 6, 2012Updated 14 years ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆19Oct 23, 2016Updated 10 years ago
- Python wrapper for Xilinx's XSCT/XSDB console☆10Nov 19, 2019Updated 6 years ago