Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
☆40Jan 22, 2026Updated 7 months ago
Alternatives and similar repositories for myhdlpeek
Users that are interested in myhdlpeek are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 12 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆92Jul 7, 2021Updated 5 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 13 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 14 years ago
- nMigen support for Xilinx Zynq devices☆17Nov 5, 2022Updated 3 years ago
- Educational materials and tooling for digital HDL synthesis in Python with myHDL☆36Sep 24, 2018Updated 7 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆18Feb 20, 2020Updated 6 years ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 6800 CPU written in nMigen☆49Jun 16, 2021Updated 5 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆87Dec 23, 2018Updated 7 years ago
- MyHDL hardware design language encased in the tasty PygMyHDL wrapper.☆19Jan 22, 2026Updated 7 months ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- Library of componentes for PySpice☆13Oct 15, 2019Updated 6 years ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆19Oct 23, 2016Updated 9 years ago
- A Pistorm CPU board replacement☆21Dec 7, 2024Updated last year
- ☆64Jul 21, 2020Updated 6 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CLI for WaveDrom☆68Feb 22, 2024Updated 2 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Aug 9, 2026Updated 3 weeks ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆35Jul 15, 2024Updated 2 years ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 8 years ago
- A pipelined MIPS processor implemented in Python☆25Mar 31, 2016Updated 10 years ago
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Sep 2, 2023Updated 3 years ago
- Model zoo for the Quantized ONNX (QONNX) model format☆15Oct 31, 2025Updated 10 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆29Apr 3, 2019Updated 7 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆22Jul 22, 2024Updated 2 years ago
- LiteX project for the ButterStick bootloader☆14Mar 13, 2023Updated 3 years ago
- ☆10Jul 6, 2015Updated 11 years ago
- Reed-Solomon Coding with Interleaving , available as a C program and python module.☆10Jun 2, 2015Updated 11 years ago
- A Python interface to the MAGMA libraries☆10Sep 3, 2016Updated 9 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆688Jan 8, 2022Updated 4 years ago