perehinik / SDRAM_Controller
Verilog SDR SDRAM controller for FPGA Xilinx and Lattice
☆16Updated 4 years ago
Alternatives and similar repositories for SDRAM_Controller:
Users that are interested in SDRAM_Controller are comparing it to the libraries listed below
- ☆13Updated last year
- Vivado project for Xilinx Artix FPGA, used in logic analyzer☆13Updated 3 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 2 months ago
- PCI bridge☆18Updated 10 years ago
- Wishbone interconnect utilities☆39Updated 2 months ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆15Updated 2 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆11Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- ☆30Updated 8 years ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆20Updated last year
- simple hyperram controller☆11Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- USB Full Speed PHY☆44Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- ☆15Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆54Updated last year
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 3 years ago
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆21Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated last year
- Fusesoc compatible rtl cores☆15Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 11 months ago