Alternatives and similar repositories for SDRAM_Controller

Users that are interested in SDRAM_Controller are comparing it to the libraries listed below

• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆51Updated 7 months ago
• RobRoyce / fpga_mouse_controller_basys3
  USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and valid…
  ☆17Updated 3 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆86Updated last year
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last week
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆39Updated last month
• briansune / Delta-Sigma-DAC-Verilog
  Delta Sigma DAC FPGA
  ☆47Updated 11 months ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆16Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆79Updated 3 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆91Updated 5 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆39Updated 7 years ago
• SpinalHDL / SpinalDoc
  SpinalHDL documentation assets (pictures, slides, ...)
  ☆32Updated last year
• nhandyal / Verilog-Spectrum-Analyzer
  FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
  ☆14Updated 13 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆76Updated 2 years ago
• chiselverify / vhdl2verilog
  ☆19Updated 5 years ago
• taneroksuz / rv-diios
  6-stage dual-issue in-order superscalar risc-v cpu with floating point unit
  ☆14Updated this week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆33Updated 5 months ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• ldoolitt / vhd2vl
  ☆140Updated this week
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆44Updated 11 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 8 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆77Updated last week
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆18Updated 7 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆93Updated last year
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆40Updated 5 months ago
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆15Updated 3 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆32Updated 10 years ago