Alternatives and similar repositories for tt09:

Users that are interested in tt09 are comparing it to the libraries listed below

• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆70Updated this week
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆39Updated 2 years ago
• MichaelBell / nanoV
  RISC-V RV32E core designed for minimal area
  ☆14Updated 5 months ago
• robtaylor / amaranth-awesome
  Awesome projects using the Amaranth HDL
  ☆13Updated 2 months ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated last week
• lawrie / ulx3s_zx_spectrum
  Minimal ZX Spectrum for Ulx3s ECP5 board
  ☆12Updated 4 years ago
• FPGAOL-CE / osstoolchain-docker-things
  Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more
  ☆13Updated 2 weeks ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆38Updated 4 months ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 2 weeks ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆59Updated 3 years ago
• YoWASP / nextpnr
  Unofficial nextpnr WebAssembly packages
  ☆16Updated this week
• stefanpie / sa-placer
  ☆14Updated last year
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 6 months ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 9 months ago
• antonblanchard / ghdl-yosys-blink
  Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr
  ☆26Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆90Updated 7 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆14Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated last week
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 3 years ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated 2 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last week
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year