Alternatives and similar repositories for myhdl_lib

Users that are interested in myhdl_lib are comparing it to the libraries listed below

• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆72Updated 10 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 9 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆60Updated last month
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆88Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆89Updated 6 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• CospanDesign / python-pci
  Python interface to PCIE
  ☆39Updated 7 years ago
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆37Updated 3 weeks ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 11 months ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 7 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆107Updated last year
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆62Updated 3 weeks ago
• open-design / riscv-soc-cores
  ☆38Updated 4 years ago