athlaing / CNNLinks
An Assortment of Convolutional Neural Networks
☆11Updated 6 years ago
Alternatives and similar repositories for CNN
Users that are interested in CNN are comparing it to the libraries listed below
Sorting:
- ☆12Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- ☆65Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- ☆112Updated 4 years ago
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆143Updated last month
- Vitis HLS Library for FINN☆198Updated 3 weeks ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆195Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆83Updated 3 years ago
- ☆94Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆155Updated 5 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆110Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 5 months ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- IC implementation of TPU☆124Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago