secworks / sha3Links
FIPS 202 compliant SHA-3 core in Verilog
☆23Updated 5 years ago
Alternatives and similar repositories for sha3
Users that are interested in sha3 are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- ☆81Updated last year
- ☆20Updated 5 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Verilog implementation of the SHA-512 hash function.☆42Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Chisel implementation of AES☆23Updated 5 years ago
- ☆29Updated 8 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆27Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆13Updated 10 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- Chisel Cheatsheet☆34Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- ☆67Updated 2 years ago
- Chisel Fixed-Point Arithmetic Library☆16Updated 11 months ago