secworks / sha3Links
FIPS 202 compliant SHA-3 core in Verilog
☆22Updated 5 years ago
Alternatives and similar repositories for sha3
Users that are interested in sha3 are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆33Updated last year
- ☆80Updated last year
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Chisel implementation of AES☆23Updated 5 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Defense/Attack PUF Library (DA PUF Library)☆51Updated 5 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- This script generates and analyzes prefix tree adders.☆39Updated 4 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆20Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…☆24Updated 3 years ago
- ☆29Updated 8 years ago
- Hardware implementation of ORAM☆22Updated 8 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 11 months ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆18Updated 3 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 3 years ago
- A vector processor implemented in Chisel☆21Updated 11 years ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆23Updated 4 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆35Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago