secworks / sha3Links
FIPS 202 compliant SHA-3 core in Verilog
☆23Updated 5 years ago
Alternatives and similar repositories for sha3
Users that are interested in sha3 are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆35Updated last year
- ☆81Updated last year
- Chisel implementation of AES☆23Updated 5 years ago
- ☆20Updated 5 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- CNN accelerator☆27Updated 8 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆27Updated last year
- FFT generator using Chisel☆62Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆67Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆36Updated 3 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆92Updated last year
- LIS Network-on-Chip Implementation☆33Updated 9 years ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- ☆29Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago