pgroupATusc / fasthashLinks
Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
☆25Updated 3 years ago
Alternatives and similar repositories for fasthash
Users that are interested in fasthash are comparing it to the libraries listed below
Sorting:
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆22Updated 2 years ago
- ☆26Updated 4 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆69Updated 9 months ago
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- corundum work on vu13p☆21Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 9 years ago
- Distributed Accelerator OS☆64Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 6 years ago
- ☆27Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆78Updated 11 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago
- ☆27Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- Framework for FPGA-accelerated Middlebox Development☆47Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- This repo contains the Limago code☆87Updated 5 months ago
- ☆67Updated 4 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆18Updated 6 years ago
- ☆24Updated 4 years ago
- Public release☆56Updated 6 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- AMD OpenNIC Shell includes the HDL source files☆131Updated 9 months ago
- BlackParrot on Zynq☆48Updated this week