Alternatives and similar repositories for aes128-hdl

Users that are interested in aes128-hdl are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 9 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆57Updated 2 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆57Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆48Updated 9 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• verilator / example-systemverilog
  ☆38Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆103Updated 2 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated 2 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆54Updated 3 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆15Updated last year