Alternatives and similar repositories for srio-controller

Users that are interested in srio-controller are comparing it to the libraries listed below

• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆156Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆216Updated 2 years ago
• suisuisi / FPGAandImage
  image processing based FPGA
  ☆115Updated 4 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆34Updated 3 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆67Updated 7 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆194Updated last year
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆51Updated 2 years ago
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆44Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆50Updated 5 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆171Updated 3 years ago
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆142Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆70Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆211Updated 2 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• eepro-bt / documents
  文档编写
  ☆13Updated 5 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆147Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆125Updated 5 months ago
• WangXuan95 / UH-JLS
  An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。
  ☆101Updated last year
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• WangXuan95 / FPGA-LZMA-compressor
  An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。
  ☆88Updated 2 years ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆47Updated 4 years ago
• WangXuan95 / Zynq-Tutorial
  使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
  ☆117Updated last year
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆218Updated 2 months ago
• Anthon1e / 8B-10B-Encoder-Decoder
  8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC-balance and bounded disparity, which is used for telecommunic…
  ☆11Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆73Updated 9 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆81Updated 5 years ago