CospanDesign / verilog-visualizerLinks
A GUI to help users visualize the structure of a verilog HDL project
☆12Updated 10 years ago
Alternatives and similar repositories for verilog-visualizer
Users that are interested in verilog-visualizer are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆61Updated 2 years ago
- Wishbone controlled I2C controllers☆55Updated last year
- Digital Circuit rendering engine☆39Updated 4 months ago
- Utilities for MyHDL☆19Updated last year
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- VHDL Modules☆24Updated 10 years ago
- Wishbone to AXI bridge (VHDL)☆43Updated 6 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Updated last year
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- GUI editor for hardware description designs☆30Updated 2 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 9 years ago
- ☆19Updated last year
- Open Source ZYNQ Board☆31Updated 10 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- ☆20Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated last week
- WCH CH569 SerDes Reverse Engineering☆28Updated 3 years ago
- Implemented The UART with FIFO☆15Updated 6 years ago
- Digital FM Radio Receiver for FPGA☆63Updated 9 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Small footprint and configurable JESD204B core☆49Updated last month
- micropython ESP32 programmer/flasher for ECP5 JTAG☆74Updated 3 months ago
- Example code in Verilog for the Blackice II FPGA☆28Updated 6 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13Updated 10 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆50Updated 12 years ago
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Updated 7 years ago