ZipCPU / tttt
A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms
☆9Updated 7 years ago
Alternatives and similar repositories for tttt:
Users that are interested in tttt are comparing it to the libraries listed below
- A wishbone controlled FM transmitter hack☆21Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A bit-serial CPU☆18Updated 5 years ago
- "Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.☆18Updated 5 years ago
- VGA-compatible text mode functionality☆16Updated 4 years ago
- CMod-S6 SoC☆40Updated 7 years ago
- ☆51Updated 7 years ago
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆34Updated 6 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆12Updated 5 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆16Updated 6 years ago
- SNES for MiSTer☆15Updated 4 years ago
- Enigma in FPGA☆29Updated 5 years ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14Updated 4 years ago
- Amber ARM-compatible core☆13Updated 10 years ago
- sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility☆30Updated 2 months ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated 3 months ago
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 4 years ago
- The binaries for SaxonSoc Linux and other configurations☆17Updated 2 years ago
- XC2064 bitstream documentation☆16Updated 6 years ago
- Mega/Xmega soft core RTL design.☆11Updated 5 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆31Updated 8 years ago
- This is a higan/Verilator co-simulation example/framework☆49Updated 6 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- A highly-configurable and compact variant of the ZPU processor core☆34Updated 9 years ago
- A Real Time Clock core for FPGA's☆23Updated last year
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs☆34Updated 4 months ago
- A ZipCPU demonstration port for the icoboard☆17Updated 3 years ago
- An experimental CPU design☆15Updated 5 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12Updated 4 years ago