Alternatives and similar repositories for librecores-ci-jenkins-server

Users that are interested in librecores-ci-jenkins-server are comparing it to the libraries listed below

• librecores / docker-images
  CI Docker Images
  ☆19Updated 4 years ago
• librecores / librecores-web
  LibreCores Web Site
  ☆35Updated 2 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• syntacore / fpga-sdk-prj
  FPGA-based SDK projects for SCRx cores
  ☆18Updated 3 years ago
• fusesoc / fusesoc.github.io
  ☆20Updated last year
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆107Updated 5 years ago
• google / skywater-pdk-libs-sky130_fd_sc_hd
  "High density" digital standard cells for SKY130 provided by SkyWater.
  ☆16Updated 2 years ago
• amromanov / vmodel
  Vmodel toolbox repository
  ☆14Updated 9 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆37Updated 4 years ago
• riscv / riscv-smbios
  RISC-V SMBIOS Type 44 Spec
  ☆12Updated last year
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆52Updated last year
• f4pga / f4pga
  Documentation for F4PGA
  ☆23Updated last year
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆74Updated 6 months ago
• byuccl / tincr
  A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite
  ☆42Updated 5 years ago
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆86Updated 3 years ago
• pvdissel / talk-jenkins-jobdsl
  "Cultivating the Jenkins job jungle with Groovy" presentation repository
  ☆12Updated 10 years ago
• jck / uhdl
  Utilities for MyHDL
  ☆18Updated last year
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆48Updated 9 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆38Updated 8 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated 3 weeks ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 8 years ago
• jenkinsci / workflow-scm-step-plugin
  ☆42Updated this week
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• chiphackers / covered
  Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…
  ☆31Updated 6 years ago
• cjdrake / AES
  Advanced Encryption Standard (AES) SystemVerilog Core
  ☆34Updated 7 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆84Updated 4 years ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆34Updated 6 months ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 8 months ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated 6 months ago