WangXuan95 / FPGA-Gzip-compressor
An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。
☆114Updated last year
Alternatives and similar repositories for FPGA-Gzip-compressor:
Users that are interested in FPGA-Gzip-compressor are comparing it to the libraries listed below
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆80Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆95Updated last year
- An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器,可以从PNG文件中解码出原始像素。☆90Updated last year
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆168Updated last year
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。☆92Updated 6 months ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆67Updated last year
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆170Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆121Updated last year
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- ☆57Updated 2 years ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆97Updated 6 months ago
- AXI总线连接器☆97Updated 5 years ago
- An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来…☆83Updated last year
- ARM中通过APB总线连接的UART模块☆63Updated 5 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- DDR2 memory controller written in Verilog☆74Updated 13 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- ☆56Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆175Updated last year
- AXI Interface Nand Flash Controller (Sync mode)☆91Updated 7 months ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- 视频旋转(2019FPGA大赛)☆33Updated 4 years ago
- ☆36Updated 9 years ago
- Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。☆107Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆114Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆139Updated last month