tomtor / HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
☆60Updated 6 years ago
Alternatives and similar repositories for HDL-deflate:
Users that are interested in HDL-deflate are comparing it to the libraries listed below
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- ☆56Updated 4 years ago
- Altera Advanced Synthesis Cookbook 11.0☆103Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Mathematical Functions in Verilog☆92Updated 4 years ago
- Ethernet interface modules for Cocotb☆63Updated last year
- Ethernet switch implementation written in Verilog☆47Updated last year
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- round robin arbiter☆73Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- PCI Express controller model☆56Updated 2 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆70Updated 2 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆155Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 6 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 8 months ago
- Extensible FPGA control platform☆60Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated this week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Verilog digital signal processing components☆134Updated 2 years ago