tomtor / HDL-deflateLinks
FPGA implementation of deflate (de)compress RFC 1950/1951
☆62Updated 6 years ago
Alternatives and similar repositories for HDL-deflate
Users that are interested in HDL-deflate are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- IP operations in verilog (simulation and implementation on ice40)☆58Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 3 weeks ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- Xilinx Unisim Library in Verilog☆82Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Mathematical Functions in Verilog☆93Updated 4 years ago
- A simple DDR3 memory controller☆58Updated 2 years ago
- Ethernet interface modules for Cocotb☆68Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated 11 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆66Updated 8 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 2 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆29Updated last year
- SpinalHDL Hardware Math Library☆89Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- ☆63Updated 4 years ago