tomtor / HDL-deflateLinks
FPGA implementation of deflate (de)compress RFC 1950/1951
☆63Updated 6 years ago
Alternatives and similar repositories for HDL-deflate
Users that are interested in HDL-deflate are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆118Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last month
- A simple DDR3 memory controller☆61Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- Ethernet interface modules for Cocotb☆71Updated 3 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- UART models for cocotb☆32Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 3 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- ☆69Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆32Updated last year