open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
☆737Updated 3 months ago
Alternatives and similar repositories for openwifi-hw:
Users that are interested in openwifi-hw are comparing it to the libraries listed below
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆402Updated 2 years ago
- HDL libraries and projects☆1,595Updated this week
- The USRP™ Hardware Driver FPGA Repository☆278Updated 3 years ago
- open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software☆4,050Updated this week
- Various HDL (Verilog) IP Cores☆748Updated 3 years ago
- 基于ZYNQ+AD9363的开源SDR硬件☆466Updated 2 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆108Updated this week
- The RIFFA development repository☆804Updated 9 months ago
- VeeR EH1 core☆858Updated last year
- Verilog PCI express components☆1,236Updated 10 months ago
- Verilog UART☆455Updated 2 weeks ago
- Bus bridges and other odds and ends☆523Updated last month
- Small footprint and configurable PCIe core☆521Updated this week
- Verilog I2C interface for FPGA implementation☆584Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆789Updated 2 weeks ago
- ☆605Updated 8 months ago
- Must-have verilog systemverilog modules☆1,731Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,633Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,234Updated 2 weeks ago
- Example designs for FPGA Drive FMC☆237Updated 2 months ago
- Universal utility for programming FPGA☆1,281Updated this week
- Verilog library for ASIC and FPGA designers☆1,258Updated 10 months ago
- Linux on LiteX-VexRiscv☆616Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆562Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,023Updated last month
- The root repo for lowRISC project and FPGA demos.☆595Updated last year
- A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…☆486Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆312Updated 10 months ago
- A small, light weight, RISC CPU soft core☆1,365Updated last month