Alternatives and similar repositories for openwifi-hw

Users that are interested in openwifi-hw are comparing it to the libraries listed below

• jhshi / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆441Updated 2 years ago
• EttusResearch / fpga
  The USRP™ Hardware Driver FPGA Repository
  ☆292Updated 3 years ago
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,774Updated this week
• open-sdr / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆125Updated 4 months ago
• kangyuzhe666 / ZYNQ7010-7020_AD9363
  基于ZYNQ+AD9363的开源SDR硬件
  ☆529Updated 3 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆850Updated last year
• open-sdr / openwifi
  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
  ☆4,410Updated last week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,453Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆841Updated 4 years ago
• bperez77 / xilinx_axidma
  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…
  ☆521Updated 2 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆840Updated 8 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆656Updated 8 months ago
• Digilent / vivado-library
  ☆646Updated 3 months ago
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆629Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,016Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆514Updated 8 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆597Updated 7 years ago
• analogdevicesinc / linux
  Linux kernel variant from Analog Devices; see README.md for details
  ☆562Updated this week
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆459Updated last week
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,868Updated 3 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,405Updated this week
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆275Updated 10 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆603Updated 7 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆906Updated 2 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,841Updated 8 months ago
• catkira / open5G_phy
  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
  ☆214Updated 6 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,354Updated last year
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,002Updated 3 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆388Updated 2 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆665Updated 2 months ago