open-sdr / openofdmLinks
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
☆130Updated 2 months ago
Alternatives and similar repositories for openofdm
Users that are interested in openofdm are comparing it to the libraries listed below
Sorting:
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆454Updated 3 years ago
- RTL implementation of components for DVB-S2☆131Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆62Updated 6 years ago
- IEEE 802.11 OFDM-based transceiver system☆43Updated 8 years ago
- The USRP™ Hardware Driver FPGA Repository☆295Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆113Updated 2 weeks ago
- Verilog实现OFDM基带☆45Updated 10 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆129Updated last month
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆224Updated 9 months ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆51Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆59Updated 2 weeks ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆60Updated last year
- ANTSDR Firmware☆141Updated 2 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆24Updated 6 years ago
- MATLAB toolbox for ADI transceiver products☆64Updated 3 weeks ago
- Python productivity for RFSoC platforms☆88Updated 3 months ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆251Updated 2 years ago
- PYNQ-Z1 + AD936X openwifi capable SDR platform☆121Updated 7 months ago
- LTE/WiFi/5G-NR SDR Transceiver☆56Updated 7 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆26Updated last year
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆80Updated 2 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆23Updated 10 months ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆41Updated 2 weeks ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆76Updated last year
- ☆28Updated last year
- MATLAB-based FIR filter design☆62Updated last year
- IIO AD9361 library for filter design and handling, multi-chip sync, etc.☆100Updated last week
- RFSoC Spectrum Analyser Module on PYNQ.☆90Updated 2 weeks ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆89Updated last year
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆47Updated 3 months ago