RedFlag2017 / rs-codecLinks
Reed Solomon Encoder and Decoder Digital IP
☆21Updated 5 years ago
Alternatives and similar repositories for rs-codec
Users that are interested in rs-codec are comparing it to the libraries listed below
Sorting:
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆77Updated 2 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆67Updated last week
- Verilog based BCH encoder/decoder☆125Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆62Updated 3 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆58Updated last year
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 7 years ago
- verilog☆21Updated 2 years ago
- Wi-Fi LDPC codec Verilog IP core☆18Updated 6 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆31Updated 4 years ago
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆52Updated 8 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 6 years ago
- Gaussian noise generator Verilog IP core☆32Updated 2 years ago
- Hardware Viterbi Decoder in verilog☆27Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆38Updated 4 years ago
- ☆26Updated 4 months ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆28Updated 5 years ago
- ☆79Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆59Updated 3 years ago
- An AXI DDR3 SDRAM controller for FPGA☆41Updated last year
- FIR implemention with Verilog☆49Updated 6 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆15Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- 基于FPGA的FFT☆19Updated 6 years ago