Alternatives and similar repositories for LDPC_MS

Users that are interested in LDPC_MS are comparing it to the libraries listed below

• Hyacinth2333 / QC_LDPC-ECC
  NMS_decode
  ☆14Updated 5 years ago
• biren15 / Design-and-Verification-of-LDPC-Decoder
  - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …
  ☆54Updated 8 years ago
• adimitris / verilog-LDPC-decoder
  A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)
  ☆11Updated 5 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆24Updated 6 years ago
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆18Updated 6 years ago
• ziruizhu / ofdm
  Toy OFDM Communication System with FPGA
  ☆12Updated 4 years ago
• hhping / LDPC_en-decoder
  LDPC编码解码matlab代码和Verilog代码及资料
  ☆47Updated 7 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆61Updated 9 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆80Updated 2 years ago
• aq12138 / Git_Bilbili
  verilog
  ☆21Updated 2 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆129Updated last month
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆29Updated 6 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆58Updated 4 years ago
• Spartak0s / Polar-Codes-Hardware-VHDL
  Polar Codes Implementation on Vhdl
  ☆15Updated 9 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆54Updated last year
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆132Updated 3 years ago
• wudayemen / gen_apb_file
  ☆75Updated 4 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆160Updated 6 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆30Updated 11 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆60Updated 2 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆71Updated last year
• C-H-Chien / FPGA_SIFT-LES
  Integration of SIFT and LES Algorithms
  ☆14Updated last year
• CY0807 / BRAM_DDR3_HDMI
  在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。
  ☆30Updated 3 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆60Updated last year
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆64Updated 3 years ago
• lauchinyuan / Asymmetric_async_FIFO
  asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…
  ☆26Updated 2 years ago
• wangyuxiao2000 / ccsds-ldpc
  ccsds ldpc encdoer and decoder.(CCSDS 131.1-O-2)
  ☆24Updated last year