gnuradio / gr-verilog
☆17Updated 2 years ago
Alternatives and similar repositories for gr-verilog
Users that are interested in gr-verilog are comparing it to the libraries listed below
Sorting:
- LiteX Accelerator Block for GNU Radio☆24Updated 3 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 weeks ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated 3 weeks ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆29Updated 2 years ago
- ☆30Updated 4 years ago
- Saturn SDR Radio: Xilinx FPGA and Raspberry Pi 4 CM☆41Updated 2 weeks ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- Digital FM Radio Receiver for FPGA☆60Updated 9 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- RISC-V System on Chip Builder☆12Updated 4 years ago
- ☆16Updated 6 months ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- ☆18Updated 4 years ago
- A padring generator for ASICs☆25Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- Extensible FPGA control platform☆60Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- LimeSDR XTRX gateware project.☆16Updated 3 months ago
- An open-source VHDL library for FPGA design.☆31Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆44Updated last year
- Single Port RAM, Dual Port RAM, FIFO☆24Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago