ChinaQMTECH / ZYJZGW_Kintex-7_XC7K325T_Starter_Kit
☆17Updated 3 years ago
Alternatives and similar repositories for ZYJZGW_Kintex-7_XC7K325T_Starter_Kit:
Users that are interested in ZYJZGW_Kintex-7_XC7K325T_Starter_Kit are comparing it to the libraries listed below
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- ☆36Updated 3 years ago
- Wishbone interconnect utilities☆38Updated last week
- USB Full Speed PHY☆39Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- Wishbone controlled I2C controllers☆45Updated 3 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆42Updated 3 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆22Updated 4 months ago
- Extensible FPGA control platform☆57Updated last year
- Verilog Repository for GIT☆31Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Single Port RAM, Dual Port RAM, FIFO☆21Updated 2 years ago
- Collection of projects for various FPGA development boards☆43Updated 9 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 10 months ago
- USB serial device (CDC-ACM)☆37Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Small footprint and configurable JESD204B core☆41Updated last month
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- SDRAM controller for MIPSfpga+ system☆22Updated 4 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆60Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆59Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year