Alternatives and similar repositories for riscv_cpu

Users that are interested in riscv_cpu are comparing it to the libraries listed below

• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆66Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆117Updated 3 weeks ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆150Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• ChunxuGuo / SummerSchool2022
  ☆61Updated 2 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• pulp-platform / fpu
  ☆49Updated 6 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆115Updated 12 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• ytliu74 / RISCV_Verilog
  RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
  ☆19Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆154Updated 3 weeks ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆110Updated 11 months ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆59Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆59Updated 3 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• CustomizableComputingLab / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆15Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆23Updated last year
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 9 months ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆17Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆37Updated 4 years ago