secure-foundations / veri-titanLinks
Verifying OpenTitan
☆26Updated last year
Alternatives and similar repositories for veri-titan
Users that are interested in veri-titan are comparing it to the libraries listed below
Sorting:
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆33Updated 4 months ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- CHERI-RISC-V model written in Sail☆59Updated 2 months ago
- RISC-V Specification in Coq☆114Updated 4 months ago
- Galois RISC-V ISA Formal Tools☆58Updated 2 months ago
- Symbolic execution tool for Sail ISA specifications☆67Updated 2 weeks ago
- Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture☆31Updated 4 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆80Updated last week
- CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives☆62Updated 11 months ago
- Pono: A flexible and extensible SMT-based model checker☆103Updated this week
- A formal semantics of the RISC-V ISA in Haskell☆165Updated last year
- A core language for rule-based hardware design 🦑☆154Updated 7 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆154Updated 8 months ago
- Binary analysis in HOL☆40Updated 2 months ago
- rmem public repo☆42Updated 2 weeks ago
- ☆47Updated 3 years ago
- IC3PO: IC3 for Proving Protocol Properties☆27Updated 8 months ago
- Automatically generate a compiler using equality saturation☆30Updated last year
- Iodine: Verifying Constant-Time Execution of Hardware☆13Updated 4 years ago
- Verilog development and verification project for HOL4☆26Updated last month
- UCLID5: formal modeling, verification, and synthesis of computational systems☆143Updated 2 months ago
- A Tool for the Static Analysis of Cache Side Channels☆40Updated 8 years ago
- A model checker for infinite-state systems.☆74Updated 2 weeks ago
- work in progress, playing around with btor2 in rust☆11Updated 2 weeks ago
- ☆49Updated last week
- The HW-CBMC and EBMC Model Checkers for Verilog☆72Updated this week
- Automatic detection of speculative information flows☆68Updated 3 years ago
- Armv8 Native Code Symbolic Simulator in Lean☆84Updated 5 months ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆40Updated this week