someone755 / ddr3-controllerLinks
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
☆79Updated 3 years ago
Alternatives and similar repositories for ddr3-controller
Users that are interested in ddr3-controller are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆70Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 4 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆132Updated last week
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Verilog SPI master and slave☆62Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Updated last year
- ☆28Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago