someone755 / ddr3-controllerLinks
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
☆76Updated 3 years ago
Alternatives and similar repositories for ddr3-controller
Users that are interested in ddr3-controller are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆67Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆93Updated 3 years ago
- UART models for cocotb☆32Updated 3 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- ☆76Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆74Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆118Updated 4 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 2 weeks ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- ☆28Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- ☆33Updated last month
- RISC-V Nox core☆70Updated 4 months ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 10 years ago
- I2C models for cocotb☆38Updated 3 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Verilog digital signal processing components☆161Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated this week
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year