Alternatives and similar repositories for ddr3-controller

Users that are interested in ddr3-controller are comparing it to the libraries listed below

• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆78Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆93Updated 5 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆125Updated 6 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆24Updated 2 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆67Updated last week
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆55Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆54Updated 9 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆81Updated 4 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆26Updated 11 months ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago