someone755 / ddr3-controllerLinks
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
☆79Updated 3 years ago
Alternatives and similar repositories for ddr3-controller
Users that are interested in ddr3-controller are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆69Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 4 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 3 years ago
- UART models for cocotb☆32Updated 4 months ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- ☆78Updated 3 years ago
- ☆28Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆130Updated this week
- RISC-V Nox core☆71Updated 6 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- DDR2 memory controller written in Verilog☆79Updated 13 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Updated 7 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆62Updated 6 years ago
- ☆34Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Ethernet interface modules for Cocotb☆74Updated 4 months ago