aklsh / getting-started-with-verilog
Verilog modules for beginners
☆23Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for getting-started-with-verilog
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆140Updated 4 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- ☆16Updated last year
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- UVM and System Verilog Manuals☆36Updated 5 years ago
- Training Neural Networks using Analog circuits☆21Updated 3 years ago
- ☆99Updated 10 months ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆35Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆32Updated 5 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆98Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆74Updated 4 years ago
- ☆22Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆9Updated 7 months ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆32Updated 4 months ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆84Updated 3 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆15Updated 6 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- opensource EDA tool flor VLSI design☆29Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆47Updated 2 weeks ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆56Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆35Updated 11 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆212Updated 3 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆96Updated 9 months ago
- Lecture about FIR filter on an FPGA☆13Updated 6 months ago