aklsh / getting-started-with-verilogLinks
Verilog modules for beginners
☆28Updated 3 years ago
Alternatives and similar repositories for getting-started-with-verilog
Users that are interested in getting-started-with-verilog are comparing it to the libraries listed below
Sorting:
- Verilog HDL files☆149Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year
- This repo provide an index of VLSI content creators and their materials☆156Updated last year
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆265Updated 3 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆46Updated 4 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 6 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆115Updated 3 years ago
- 100 Days of RTL☆389Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆56Updated 2 years ago
- FPGA Design of a Neural Network for Color Detection☆77Updated 6 months ago
- opensource EDA tool flor VLSI design☆33Updated last year
- ☆115Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆90Updated 2 years ago
- SystemVerilog Tutorial☆166Updated 3 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆139Updated 3 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆119Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- ☆95Updated last year
- An overview of TL-Verilog resources and projects☆81Updated 5 months ago
- ☆58Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated last month
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago
- Lecture about FIR filter on an FPGA☆12Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago