aklsh / getting-started-with-verilogLinks
Verilog modules for beginners
☆28Updated 3 years ago
Alternatives and similar repositories for getting-started-with-verilog
Users that are interested in getting-started-with-verilog are comparing it to the libraries listed below
Sorting:
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆113Updated 3 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆263Updated 2 months ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- Verilog HDL files☆147Updated last year
- This repo provide an index of VLSI content creators and their materials☆154Updated 11 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆57Updated 2 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆135Updated 2 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆140Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆45Updated 4 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆73Updated 3 years ago
- ☆114Updated last year
- SystemVerilog Tutorial☆160Updated 3 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆116Updated 4 years ago
- Verilog for ASIC Design☆29Updated 3 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆59Updated 4 years ago
- 100 Days of RTL☆386Updated 11 months ago
- ☆22Updated 2 years ago
- FPGA Design of a Neural Network for Color Detection☆77Updated 6 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆104Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆141Updated 4 years ago
- An overview of TL-Verilog resources and projects☆80Updated 4 months ago
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆12Updated 3 years ago
- opensource EDA tool flor VLSI design☆33Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆89Updated 2 years ago
- Solve one design problem each day for a month☆44Updated 2 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆112Updated 2 months ago