vedic-partap / Computer-Organization-and-Architecture-LABLinks
Solution to COA LAB Assgn, IIT Kharagpur
☆36Updated 6 years ago
Alternatives and similar repositories for Computer-Organization-and-Architecture-LAB
Users that are interested in Computer-Organization-and-Architecture-LAB are comparing it to the libraries listed below
Sorting:
- ☆63Updated 4 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆58Updated 3 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆60Updated 5 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆124Updated 3 years ago
- An overview of TL-Verilog resources and projects☆82Updated last week
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆96Updated 9 months ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆116Updated 6 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆115Updated 5 years ago
- All the projects and assignments done as part of VLSI course.☆20Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Project ideas list for Google Summer of Code.☆18Updated 10 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆129Updated 2 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆166Updated last year
- ☆17Updated 2 years ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆52Updated 2 years ago
- RISC V core implementation using Verilog.☆28Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆56Updated 10 months ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum☆54Updated 4 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆284Updated 6 months ago
- 100 Days of RTL☆403Updated last year
- An 8 input interrupt controller written in Verilog.☆28Updated 13 years ago
- ☆117Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago