vedic-partap / Computer-Organization-and-Architecture-LAB

Related projects ⓘ

Alternatives and complementary repositories for Computer-Organization-and-Architecture-LAB

• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆56Updated 3 years ago
• digital-design-hq / Digital-Resources
  ☆53Updated 3 years ago
• harshithsn / Universal-Shift-Register
  This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…
  ☆10Updated 2 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆51Updated last year
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆25Updated 12 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆60Updated 5 years ago
• mihir8181 / VerilogHDL-Codes
  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
  ☆35Updated 5 years ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆21Updated 7 years ago
• merledu / Google-Summer-of-Code
  Project ideas list for Google Summer of Code.
  ☆11Updated 9 months ago
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆23Updated 6 years ago
• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆19Updated 6 years ago
• SkillSurf / systemverilog
  SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
  ☆32Updated 5 months ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆96Updated 9 months ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆98Updated 2 years ago
• semiDESIgner / 50daysRTLcode
  ☆16Updated last year
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆17Updated 4 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆55Updated 10 months ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated 2 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆27Updated 4 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆22Updated 3 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆29Updated last year
• Arjun-Narula / Traffic-Light-Controller-using-Verilog
  the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
  ☆39Updated 4 years ago
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆23Updated 5 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 2 weeks ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆26Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆27Updated 2 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆81Updated 2 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆25Updated 3 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆83Updated 3 years ago