Solution to COA LAB Assgn, IIT Kharagpur
☆37Jan 10, 2019Updated 7 years ago
Alternatives and similar repositories for Computer-Organization-and-Architecture-LAB
Users that are interested in Computer-Organization-and-Architecture-LAB are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆146Jul 17, 2022Updated 3 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- All of my Verilog_HDL codes☆11Apr 5, 2021Updated 4 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Nov 30, 2022Updated 3 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆140Apr 3, 2020Updated 5 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆27Sep 2, 2019Updated 6 years ago
- Operations Research Lab. Involves coding the various Linear Programming Problem optimization methods in C/C++.☆12Apr 19, 2017Updated 8 years ago
- [MIGRATED TO KRONOS] A webapp to serve past year records-grade distributions of IITKGP☆29Jun 15, 2024Updated last year
- Project Nephos [GSoC '18]: Automated recording, processing, and uploading of TV streams for Universities.☆21Jan 15, 2019Updated 7 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆48Jul 18, 2020Updated 5 years ago
- Solution of Complier Lab Assgn., IIT Kharagpur☆11Jan 10, 2019Updated 7 years ago
- CDC noticeboard scraper☆43Dec 4, 2025Updated 3 months ago
- Implementing Different Adder Structures in Verilog☆74Sep 3, 2019Updated 6 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- Notes, codes and resources for the course Computer Organisation and Architecture, IIT Kharagpur☆12Nov 11, 2019Updated 6 years ago
- ☆18Jun 3, 2017Updated 8 years ago
- The frontend of LTTKGP web app☆17Jan 8, 2023Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆76Oct 7, 2022Updated 3 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 7 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆27Jun 10, 2018Updated 7 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆229May 20, 2025Updated 10 months ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering☆19Feb 20, 2026Updated last month
- The mighty hero helping you build projects on top of IIT Kharagpur's academic data☆35Nov 13, 2018Updated 7 years ago
- Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals☆13Updated this week
- Python app to help you become prudent in your spendings☆30Aug 7, 2020Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- RISC V core implementation using Verilog.☆29Mar 27, 2021Updated 4 years ago
- A mini python quiz (Flask example)☆11Feb 21, 2017Updated 9 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- Lab assignments for 6.826☆11Nov 8, 2019Updated 6 years ago
- Predicting driver stress levels using Physionet's SRAD (drivedb) dataset with methods such as LSTMs, RNNs, CNNs☆18Mar 30, 2023Updated 2 years ago
- A collection of my cources, lectures, articles and presentations☆17Jun 25, 2019Updated 6 years ago
- A curated list of awesome development tools and resources for software developers.☆25Nov 27, 2025Updated 3 months ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- Curriculum vitae of Lester James V. Miranda☆10Jan 13, 2026Updated 2 months ago