Alternatives and similar repositories for kanagawa

Users that are interested in kanagawa are comparing it to the libraries listed below

• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆148Updated last week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆166Updated last month
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆160Updated this week
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆96Updated 3 weeks ago
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆54Updated last month
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆114Updated 2 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆249Updated 3 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆92Updated 2 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• cucapra / filament
  Fearless hardware design
  ☆185Updated 4 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆37Updated 4 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆175Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆35Updated 3 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• najaeda / naja-verilog
  A standalone structural (gate-level) verilog parser
  ☆40Updated 3 weeks ago
• tenstorrent / whisper
  ☆72Updated 3 weeks ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆54Updated last month
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 6 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated last week