spade-lang / spadeLinks
A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spade/
β39Updated this week
Alternatives and similar repositories for spade
Users that are interested in spade are comparing it to the libraries listed below
Sorting:
- π¦ No-nonsense hardware testing/simulation in Rust π οΈ | Verilog, Spade, Verylβ82Updated 3 weeks ago
- Fearless hardware designβ186Updated 5 months ago
- Verilator Porcelainβ49Updated 2 years ago
- A new Hardware Design Language that keeps you in the driver's seatβ122Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.β105Updated last week
- RISCV Core written in Calyxβ17Updated last year
- 21st century electronic design automation tools, written in Rust.β33Updated last week
- A Hardware Description Language based on the Rust Programming Languageβ272Updated last week
- Logic circuit analysis and optimizationβ45Updated 4 months ago
- Read and write VCD (Value Change Dump) files in Rustβ44Updated last year
- The LLHD reference simulator.β39Updated 5 years ago
- A hardware compiler based on LLHD and CIRCTβ265Updated 6 months ago
- An HDL embedded in Rust.β202Updated 2 years ago
- End-to-end synthesis and P&R toolchainβ94Updated last month
- Easy SMT solver interactionβ34Updated 5 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.β19Updated 3 years ago
- Beautiful Digital Timing Diagrams with Rustβ88Updated last year
- A simple digital waveform viewer with vi-like key bindings.β143Updated 10 months ago
- β16Updated this week
- HDL development environment on Nix.β26Updated last year
- Native Rust implementation of the FST waveform format from GTKWave.β13Updated this week
- Using e-graphs to synthesize netlists from boolean logic.β14Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.β15Updated last year
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protβ¦β95Updated this week
- Unofficial Yosys WebAssembly packagesβ75Updated this week
- Scope Graph Implementation in Rustβ28Updated last year
- Verilog ASTβ21Updated 2 years ago
- A core language for rule-based hardware design π¦β167Updated last month
- β30Updated 3 years ago
- Verik toolchainβ45Updated 3 years ago