nmoroze / kronosLinks
My MEng thesis code - verifying a security property for an SoC with Rosette
☆17Updated 3 years ago
Alternatives and similar repositories for kronos
Users that are interested in kronos are comparing it to the libraries listed below
Sorting:
- Simple RISC-V processor for FPGAs☆20Updated 2 years ago
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆33Updated 4 months ago
- Tools for reasoning about circuits in Rosette/Racket 🔌☆19Updated 4 months ago
- FPGA synthesis tool powered by program synthesis☆49Updated 2 weeks ago
- Iodine: Verifying Constant-Time Execution of Hardware☆13Updated 4 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- FPGA synthesis tool powered by equality saturation and program synthesis.☆12Updated last month
- BTOR2 MLIR project☆25Updated last year
- Code repository for Coppelia tool☆23Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- PipeProof☆11Updated 5 years ago
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- work in progress, playing around with btor2 in rust☆11Updated 2 weeks ago
- The PE for the second generation CGRA (garnet).☆17Updated last month
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- RTLCheck☆22Updated 6 years ago
- A tool for formally verifying constant-time software against hardware 🕰️☆10Updated 4 months ago
- ☆13Updated 4 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆11Updated 11 months ago
- RISC-V BSV Specification☆20Updated 5 years ago
- ☆19Updated 10 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆14Updated 6 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 2 weeks ago
- A Hardware Pipeline Description Language☆44Updated last year
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated last year
- ☆13Updated 4 years ago
- Equivalence checking with Yosys☆43Updated last month
- A Verilog Synthesis Regression Test☆37Updated last year