nmoroze / kronosLinks
My MEng thesis code - verifying a security property for an SoC with Rosette
☆17Updated 4 years ago
Alternatives and similar repositories for kronos
Users that are interested in kronos are comparing it to the libraries listed below
Sorting:
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- BTOR2 MLIR project☆26Updated last year
- Code repository for Coppelia tool☆23Updated 5 years ago
- FPGA synthesis tool powered by program synthesis☆53Updated last week
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- RTLCheck☆23Updated 7 years ago
- Testing processors with Random Instruction Generation☆50Updated last month
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆40Updated 3 weeks ago
- PipeProof☆11Updated 6 years ago
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- design and verification of asynchronous circuits☆42Updated last week
- The HW-CBMC and EBMC Model Checkers for Verilog☆99Updated this week
- ☆19Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- ☆13Updated 4 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Updated 3 months ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Updated 5 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Updated 4 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- ☆20Updated last year
- ☆21Updated this week
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated 2 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆96Updated last week
- ☆30Updated 3 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- The SoC used for the beta phase of Hack@DAC 2018.☆18Updated 5 years ago
- Fluid Pipelines☆11Updated 7 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year