Alternatives and similar repositories for ibex_wb

Users that are interested in ibex_wb are comparing it to the libraries listed below

• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆72Updated 9 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆146Updated 6 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆78Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated 2 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆94Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated 2 weeks ago
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆93Updated last year
• jamieiles / uart
  Verilog UART
  ☆183Updated 12 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆99Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆149Updated this week
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 10 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆90Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated 2 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆144Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆117Updated 2 weeks ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆156Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆62Updated 2 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆40Updated 5 years ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆96Updated 3 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 4 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago