☆23Jun 28, 2022Updated 3 years ago
Alternatives and similar repositories for Verilog-Template
Users that are interested in Verilog-Template are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Apr 12, 2023Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 7 years ago
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- spi memory controller☆24Jan 5, 2017Updated 9 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆29Mar 13, 2025Updated last year
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆86Oct 2, 2019Updated 6 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 2 years ago
- Ethernet 10GE MAC☆46Jul 17, 2014Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- UVM verification kits which uses YASA as simulation script☆18Dec 10, 2019Updated 6 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- Python-based Verilog Parser (currently Netlist only)☆54Apr 12, 2017Updated 9 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 6 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Verilog implementation of the SHA-512 hash function.☆45Jan 17, 2026Updated 3 months ago
- UART -> AXI Bridge☆74Jul 1, 2021Updated 4 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- MIPI DSI controller☆85Jun 27, 2022Updated 3 years ago
- 一个基于ModBus RTU协议的PLC继电器从站☆11Dec 2, 2015Updated 10 years ago
- 本应用可以帮助你将国网的电费、用电量数据接入homeassistant，并且储存到数据库。☆19Sep 15, 2023Updated 2 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆37Apr 7, 2026Updated last month
- How to design a MIPI CSI interface with Efinix Trion FPGA T20F169 QUICKLY☆10Feb 6, 2020Updated 6 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 6 years ago
- A simple CANopen stack implemented using C programming language.☆11Apr 23, 2014Updated 12 years ago
- Perldoc中文译本(Perldoc Chinese Translation)☆22Apr 3, 2013Updated 13 years ago
- AMBA bus generator including AXI, AHB, and APB☆122Jul 29, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- A GitLab page server. Similar to the built-in page server, but with some additional features.☆10Jul 7, 2018Updated 7 years ago
- Verilog VGA font generator 8 by 16 pixels☆16Mar 30, 2022Updated 4 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Deprecated: replaced with https://github.com/deepin-community/deepin-wsl☆59Nov 16, 2023Updated 2 years ago