FouriersCat / Verilog-TemplateView external linksLinks
☆23Jun 28, 2022Updated 3 years ago
Alternatives and similar repositories for Verilog-Template
Users that are interested in Verilog-Template are comparing it to the libraries listed below
Sorting:
- ☆13Apr 12, 2023Updated 2 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Sep 7, 2018Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- RTL code of some arbitration algorithm☆15Aug 25, 2019Updated 6 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆24Mar 13, 2025Updated 11 months ago
- spi memory controller☆22Jan 5, 2017Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Dec 8, 2025Updated 2 months ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- UART -> AXI Bridge☆70Jul 1, 2021Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- MIPI DSI controller☆83Jun 27, 2022Updated 3 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆83Oct 2, 2019Updated 6 years ago
- This is a circular buffer controller used in FPGA.☆34Jan 12, 2016Updated 10 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆41Jun 22, 2021Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆15Sep 21, 2025Updated 4 months ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 2 years ago
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated 3 weeks ago