FouriersCat / Verilog-Template
☆23Updated 2 years ago
Alternatives and similar repositories for Verilog-Template:
Users that are interested in Verilog-Template are comparing it to the libraries listed below
- 视频旋转（2019FPGA大赛）☆31Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- ☆35Updated 9 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆17Updated 6 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- APB to I2C☆39Updated 10 years ago
- ☆16Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆66Updated 3 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆35Updated 7 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆30Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆31Updated 4 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆16Updated last year
- ☆18Updated 2 years ago
- practice configure AHB-Lite bus protocol☆11Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- amba3 apb/axi vip☆45Updated 9 years ago
- Implementation of the PCIe physical layer☆32Updated 2 weeks ago
- QSPI for SoC☆19Updated 5 years ago
- Cortex M0 based SoC☆71Updated 3 years ago
- soc integration script and integration smoke script☆20Updated 2 years ago
- Must-have verilog systemverilog modules☆30Updated 2 years ago
- UVM register utility generation by inputting xls table☆35Updated last year
- I2C Master and Slave☆32Updated 9 years ago