一些小的工程记录
☆25Feb 2, 2020Updated 6 years ago
Alternatives and similar repositories for Small_Projects
Users that are interested in Small_Projects are comparing it to the libraries listed below
Sorting:
- OpenMV交通灯图形识别☆16Jun 3, 2019Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- ☆11May 31, 2016Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- ☆14Jan 14, 2025Updated last year
- 捡球小车🏓🚗HITSZauto大一立项 | 目前可识别黄球☆11Sep 30, 2022Updated 3 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- 一个开源的基于stm32的磁悬浮项目☆15Nov 21, 2023Updated 2 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Information-enhanced Network for Noncontact Heart Rate Estimation from Facial Videos☆10Dec 12, 2023Updated 2 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- 200W 铝基板加热台控制器,具备PID控制,PWM输出,卡尔曼滤波☆11Oct 30, 2022Updated 3 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- A large-scale training and benchmarking framework for rPPG.☆10Nov 26, 2024Updated last year
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- 健康手表☆52Mar 8, 2022Updated 3 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- Wireless Industrial Condition Monitoring solution☆14Jan 17, 2025Updated last year
- ☆11Nov 3, 2021Updated 4 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- 一个配合i18n全自动生成语言库并翻译的loader☆13Jan 7, 2023Updated 3 years ago
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- Mini program multilingual☆10Jan 29, 2023Updated 3 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库!☆16May 9, 2024Updated last year
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- 使用PCA 主成分分析法。人脸识别处理方法如下:照片分组(训练+测试)+构建特征脸空间&训练+识别测试☆10Nov 23, 2018Updated 7 years ago
- This is a script for converting all Excel based formats to prettified XML format☆10Dec 13, 2017Updated 8 years ago