MadLittleMods / vga-simulatorLinks
☆17Updated 2 years ago
Alternatives and similar repositories for vga-simulator
Users that are interested in vga-simulator are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆44Updated last month
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Updated 5 years ago
- ☆140Updated this week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated last week
- A Fully Open-Source Verilog-to-PCB Flow☆26Updated last year
- A FPGA core for a simple SDRAM controller.☆123Updated 4 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 8 months ago
- VCD file (Value Change Dump) command line viewer☆120Updated 3 months ago
- HDMI Out VHDL code for 7-series Xilinx FPGAs☆63Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- A CPU on an FPGA that you can play Zork on☆51Updated 9 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Re-coded Gowin GW1N primitives for Verilator use☆21Updated 3 years ago
- Computer architecture learning environment using FPGAs☆15Updated 4 years ago
- A Video display simulator☆175Updated 8 months ago
- Zero to ASIC group submission for MPW2☆13Updated 10 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Pipelined RISC-V RV32I Core in Verilog☆41Updated 2 years ago
- Virtual Development Board☆64Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Verilog wishbone components☆124Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Updated 11 months ago
- IceChips is a library of all common discrete logic devices in Verilog☆154Updated 4 months ago
- Doom classic port to lightweight RISC‑V☆107Updated 3 years ago
- A Risc-V SoC for Tiny Tapeout☆48Updated 2 months ago