Alternatives and similar repositories for riscv-core

Users that are interested in riscv-core are comparing it to the libraries listed below

• VedantParanjape / idf-notes-sra
  https://ve0x10.in/idf-notes-sra/
  ☆13Updated 5 years ago
• BeagleWire / BeagleWire
  This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/
  ☆11Updated 4 years ago
• DeepYNet / Deepfake_Inference_On_VCK5000
  Accelerating Deepfake Inference using VCK5000 AI Inference Card
  ☆32Updated 3 years ago
• SRA-VJTI / Delta2021
  ☆17Updated 4 years ago
• SAtacker / bb-config
  Configure your beagle device
  ☆43Updated 2 years ago
• SRA-VJTI / blog
  Blog for SRA-VJTI
  ☆15Updated 2 months ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• siddharth23-8 / 32-bit-RISC-V-Cpu-Core
  ☆35Updated 3 years ago
• splinedrive / i2c_oled_fpga_bresenham
  i2c fpga oled sdd1306 bresenham implementation
  ☆14Updated 4 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆81Updated 2 years ago
• SRA-VJTI / Dimensions-v1.0
  CAD workshop focusing on SOLIDWORKS
  ☆16Updated 4 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆41Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 9 months ago
• digital-design-hq / Digital-Resources
  ☆64Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆96Updated 8 months ago
• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated 7 months ago
• stevehoover / makerchip_examples
  ☆19Updated this week
• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆24Updated 4 years ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 3 years ago
• platformio / platform-shakti
  Shakti: development platform for PlatformIO
  ☆35Updated 3 years ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆100Updated 3 years ago
• dhairyashah1 / USBee32-S2
  ☆30Updated 4 years ago
• AngeloJacobo / ULX3S_FPGA_Camera_Streaming
  Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
  ☆23Updated 4 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆27Updated 4 years ago
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 11 months ago
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆18Updated 4 years ago
• riscv-software-src / riscv-isac
  ☆32Updated last year