ombhilare999 / riscv-core
A customized RISCV core made using verilog
☆19Updated 4 years ago
Alternatives and similar repositories for riscv-core:
Users that are interested in riscv-core are comparing it to the libraries listed below
- https://ve0x10.in/idf-notes-sra/☆11Updated 4 years ago
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆11Updated 3 years ago
- ☆32Updated 3 years ago
- Blog for SRA-VJTI☆14Updated 8 months ago
- ☆1Updated 3 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Updated 3 years ago
- ☆17Updated 3 years ago
- CAD workshop focusing on SOLIDWORKS☆16Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆72Updated last year
- Configure your beagle device☆43Updated 2 years ago
- audio router using esp32☆10Updated 3 years ago
- Accelerating Deepfake Inference using VCK5000 AI Inference Card☆32Updated 2 years ago
- Image processing on FPGA using verilog☆21Updated 2 years ago
- ☆17Updated 3 weeks ago
- Notes and Assignments of embedded systems study group☆81Updated last year
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- Example of how to get started with olofk/fusesoc.☆17Updated 3 years ago
- Intuitive language for PRU which compiles down to PRU C☆69Updated 6 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 4 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆78Updated this week
- Wishbone interconnect utilities☆39Updated last month
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆25Updated 3 years ago
- M-extension for RISC-V cores.☆29Updated 4 months ago
- 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.☆100Updated last month
- This is the base repo for our graduation project in AlexU 21☆28Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- Slides and material for Xilinx bootcamp☆20Updated 3 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆72Updated this week
- Soft-microcontroller implementation of an ARM Cortex-M0☆25Updated 5 years ago
- An overview of TL-Verilog resources and projects☆77Updated 3 weeks ago