Alternatives and similar repositories for riscv-core

Users that are interested in riscv-core are comparing it to the libraries listed below

• VedantParanjape / idf-notes-sra
  https://ve0x10.in/idf-notes-sra/
  ☆12Updated 5 years ago
• BeagleWire / BeagleWire
  This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/
  ☆11Updated 3 years ago
• siddharth23-8 / 32-bit-RISC-V-Cpu-Core
  ☆33Updated 3 years ago
• SRA-VJTI / blog
  Blog for SRA-VJTI
  ☆15Updated 10 months ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• DeepYNet / Deepfake_Inference_On_VCK5000
  Accelerating Deepfake Inference using VCK5000 AI Inference Card
  ☆32Updated 2 years ago
• harshbhosale01 / image-processing-fpga
  Image processing on FPGA using verilog
  ☆23Updated 2 years ago
• SAtacker / bb-config
  Configure your beagle device
  ☆43Updated 2 years ago
• digital-design-hq / Digital-Resources
  ☆59Updated 3 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• stevehoover / makerchip_examples
  ☆19Updated last month
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• SRA-VJTI / embedded-systems-study-group
  Notes and Assignments of embedded systems study group
  ☆81Updated last year
• AngeloJacobo / ULX3S_FPGA_Camera_Streaming
  Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
  ☆21Updated 3 years ago
• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆23Updated 4 years ago
• riscv-software-src / riscv-isac
  ☆33Updated 7 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 7 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆84Updated 3 weeks ago
• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated 3 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 2 months ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆31Updated 7 months ago
• aignacio / nox
  RISC-V Nox core
  ☆64Updated 3 months ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago
• arthurbeggs / riscv-simple
  Computer architecture learning environment using FPGAs
  ☆14Updated 4 years ago
• sudhamshu091 / Hardware-Description-Languages-for-FPGA-Design
  My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
  ☆17Updated 4 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago