ombhilare999 / riscv-core
A customized RISCV core made using verilog
☆17Updated 3 years ago
Related projects: ⓘ
- https://ve0x10.in/idf-notes-sra/☆11Updated 4 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆10Updated 2 years ago
- Blog for SRA-VJTI☆13Updated last month
- ☆1Updated 3 years ago
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆11Updated 3 years ago
- ☆28Updated 2 years ago
- ☆17Updated 3 years ago
- Configure your beagle device☆41Updated last year
- Accelerating Deepfake Inference using VCK5000 AI Inference Card☆32Updated last year
- CAD workshop focusing on SOLIDWORKS☆16Updated 3 years ago
- Intuitive language for PRU which compiles down to PRU C☆67Updated 2 weeks ago
- A simple three-stage RISC-V CPU☆19Updated 3 years ago
- Pipelined RISC-V RV32I Core in Verilog☆35Updated last year
- ☆30Updated 2 years ago
- Self-balancing & line-following bot, implemented with ESP32☆13Updated 4 years ago
- Shakti: development platform for PlatformIO☆28Updated 2 years ago
- ☆10Updated 3 years ago
- Notes and Assignments of embedded systems study group☆76Updated 8 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆68Updated 10 months ago
- RISC-V Nox core☆59Updated last month
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆21Updated 3 weeks ago
- Image processing on FPGA using verilog☆20Updated last year
- RV32I single cycle simulation on open-source software Logisim.☆16Updated last year
- ☆31Updated 3 weeks ago
- A line follower simulation created in CoppeliaSim, with a C++ interface for CoppeliaSim's Remote API☆22Updated 2 years ago
- ☆34Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆34Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆21Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆54Updated this week