Hardware Agent
☆36Oct 22, 2026Updated last week
Alternatives and similar repositories for hagent
Users that are interested in hagent are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LLM Agent for Hardware Description Language☆24Jun 7, 2025Updated last year
- ☆11Feb 26, 2025Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆249Updated this week
- ☆14Aug 16, 2025Updated last year
- LintLLM is an open-source Verilog linting framework powered by Large Language Models (LLMs).☆12Aug 14, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆53Jul 22, 2026Updated 3 months ago
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated 2 years ago
- TBD☆15Feb 6, 2025Updated last year
- A mixed-signal system on chip for nanopore-based DNA sequencing☆35Nov 30, 2022Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated last year
- ☆22Aug 3, 2026Updated 2 months ago
- The ANUBIS benchmark suite for Incremental Synthesis☆13Dec 15, 2020Updated 5 years ago
- ☆39Oct 21, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆19Aug 30, 2020Updated 6 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated last year
- BaseJump Open-Source Hardware Accelerator Packages and Sockets☆12Jul 7, 2025Updated last year
- [AAAI 2025 Oral] AnalogCoder: Analog Circuit Design via Training-Free Code Generation☆211Sep 12, 2026Updated last month
- Open-source RTL logic simulator with CUDA acceleration☆305Sep 30, 2025Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆45Apr 3, 2025Updated last year
- AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.☆28Updated this week
- ☆21Sep 14, 2026Updated last month
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- CoreSmith is a Prompt to GDS Agentic Flow☆50Updated this week
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆30Jun 9, 2025Updated last year
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 6 years ago
- IDEA project source files☆115Apr 15, 2026Updated 6 months ago
- ☆61Apr 8, 2024Updated 2 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆72Oct 28, 2024Updated 2 years ago
- KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls☆13Jul 28, 2026Updated 3 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Lightweight transaction recording for SystemC☆11Oct 21, 2026Updated last week
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- Qucsator-RF is RF circuit simulation kernel for Qucs-S☆34Oct 20, 2026Updated last week
- Machine Generated Analog IC Layout☆304Apr 24, 2024Updated 2 years ago
- A Python library that reads LEF and DEF files, extract the RC parasitics and generate their corresponding SPEF file.☆19Sep 23, 2020Updated 6 years ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated last week
- Spice to Verilog Converter☆13May 23, 2023Updated 3 years ago