Alternatives and similar repositories for little-cpu

Users that are interested in little-cpu are comparing it to the libraries listed below

• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆16Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆31Updated last week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 2 weeks ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• mirekez / cpphdl
  C++ HDL (Hardware Description Language)
  ☆41Updated this week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• kagandikmen / TPU.sv
  Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
  ☆20Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 10 months ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 5 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• synogate / gatery
  Gatery, a library for circuit design.
  ☆22Updated last year
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆141Updated 2 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆27Updated 2 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 3 years ago
• riscv / riscv-test-env
  ☆51Updated 2 weeks ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated last week
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆20Updated 11 years ago
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 9 years ago