Alternatives and similar repositories for little-cpu

Users that are interested in little-cpu are comparing it to the libraries listed below

• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year
• pulp-platform / chimera
  ☆17Updated last week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 3 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 months ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆17Updated 6 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆34Updated 2 years ago
• riscv / riscv-bfloat16
  ☆35Updated last year
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆32Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated last week
• x-epic / EpicFV
  ☆20Updated 4 years ago
• blucia0a / MultiCacheSim
  A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model
  ☆27Updated 11 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• OpenXiangShan / nexus-am
  ☆35Updated last month
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆39Updated 3 months ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆29Updated last week
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• jiegec / maze-routing
  Implementation of several grid routers in Rust
  ☆13Updated 5 months ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆13Updated 3 weeks ago
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 9 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 4 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆37Updated 4 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆27Updated 3 weeks ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago