litex-hub / wishbone-utilsLinks
Utilities for working with a Wishbone bus in an embedded device
☆46Updated last month
Alternatives and similar repositories for wishbone-utils
Users that are interested in wishbone-utils are comparing it to the libraries listed below
Sorting:
- ☆44Updated 7 months ago
- Small footprint and configurable SPI core☆44Updated last week
- Small footprint and configurable Inter-Chip communication cores☆62Updated last week
- Example litex Risc-V SOC and some example code projects in multiple languages.☆69Updated 2 years ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Simplified environment for litex☆14Updated 5 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 4 months ago
- Low-cost ECP5 FPGA development board☆80Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- CRUVI Standard Specifications☆19Updated last year
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- Using the TinyFPGA BX USB code in user designs☆51Updated 6 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 11 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 3 weeks ago
- USB Full-Speed core written in migen/LiteX☆17Updated 6 years ago
- Miscellaneous ULX3S examples (advanced)☆80Updated 3 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- FPGA Odysseus with ULX3S☆68Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated 2 weeks ago
- ice40 USB Analyzer☆58Updated 5 years ago
- Nitro USB FPGA core☆87Updated last year
- Ultimate ECP5 development board☆114Updated 6 years ago