litex-hub / wishbone-utilsLinks
Utilities for working with a Wishbone bus in an embedded device
☆46Updated 2 months ago
Alternatives and similar repositories for wishbone-utils
Users that are interested in wishbone-utils are comparing it to the libraries listed below
Sorting:
- ☆44Updated 7 months ago
- Small footprint and configurable SPI core☆45Updated 2 weeks ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- Simplified environment for litex☆14Updated 5 years ago
- CRUVI Standard Specifications☆19Updated last year
- Example litex Risc-V SOC and some example code projects in multiple languages.☆70Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆65Updated 2 weeks ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated 11 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- verilog core for ws2812 leds☆33Updated 3 years ago
- Low-cost ECP5 FPGA development board☆80Updated 5 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- Ethernet PHY PMOD (Microchip LAN8720A PHY)☆47Updated 3 years ago
- Utilities for the ECP5 FPGA☆17Updated 4 years ago
- Miscellaneous ULX3S examples (advanced)☆81Updated 4 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- ice40 USB Analyzer☆57Updated 5 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 4 years ago
- Siglent SDS1x0xX-E FPGA bitstreams☆42Updated 10 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆40Updated 4 years ago
- Use ECP5 JTAG port to interact with user design☆31Updated 4 years ago
- FPGA Odysseus with ULX3S☆68Updated 2 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 5 months ago
- Nitro USB FPGA core☆86Updated last year