anuejn / 2d5
reverse engineering the canon 5D mark II (5D2) image sensor
☆17Updated last week
Alternatives and similar repositories for 2d5:
Users that are interested in 2d5 are comparing it to the libraries listed below
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆18Updated this week
- ECP5 FPGA in an "S7 Mini" form factor☆79Updated 3 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆12Updated 6 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆29Updated last year
- A opensource PCIe 3.0 Hub design based on ASM2806 with Raspberry Pi 5's PCIe FPC connector design☆53Updated 4 months ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆22Updated last year
- Open source 1080p60Hz USB & IP camera based on Sochip s3 and OS05A10/OS05A20 (general MIPI CSI IP camera interface).☆50Updated 2 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆14Updated 3 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Updated 6 years ago
- a USB2 highspeed device core, written in amaranth HDL☆46Updated 6 months ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆32Updated last year
- Change part number or package in a Xilinx 7-series FPGA bitstream☆37Updated 4 years ago
- My pergola FPGA projects☆30Updated 3 years ago
- iCE40UP5K in an Adafruit Feather form factor☆23Updated 2 years ago
- High Speed Data Acquisition over HDMI - FPGA implementation☆39Updated last week
- ☆16Updated last year
- Sodimm components for KiCad☆35Updated 4 years ago
- Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs☆107Updated 3 years ago
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- Nitro USB FPGA core☆84Updated last year
- Siglent SDS1x0xX-E FPGA bitstreams☆41Updated 3 months ago
- USB DFU bootloader gateware / firmware for FPGAs☆65Updated 5 months ago
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated 11 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆37Updated 4 months ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- PCB for ULX4M FPGA R&D board☆50Updated 2 weeks ago
- FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display☆20Updated 7 years ago
- PCIe to .1 inch header breakout☆11Updated 4 years ago