anuejn / 2d5
reverse engineering the canon 5D mark II (5D2) image sensor
☆18Updated 3 weeks ago
Alternatives and similar repositories for 2d5
Users that are interested in 2d5 are comparing it to the libraries listed below
Sorting:
- ECP5 FPGA in an "S7 Mini" form factor☆79Updated 3 years ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆32Updated last year
- Change part number or package in a Xilinx 7-series FPGA bitstream☆38Updated 5 years ago
- A opensource PCIe 3.0 Hub design based on ASM2806 with Raspberry Pi 5's PCIe FPC connector design☆57Updated 6 months ago
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- The open-source Zynq 7000 BSP generator for openXC7☆33Updated 3 months ago
- Playground for experimenting with and sharing short Amaranth programs on the web☆15Updated this week
- My pergola FPGA projects☆30Updated 3 years ago
- Miscellaneous ULX3S examples (advanced)☆77Updated 2 months ago
- DVI video out example for prjtrellis☆16Updated 6 years ago
- ☆13Updated 8 months ago
- a USB2 highspeed device core, written in amaranth HDL☆46Updated 8 months ago
- assorted library of utility cores for amaranth HDL☆88Updated 8 months ago
- 妖刀夢渡☆59Updated 6 years ago
- riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way☆62Updated 2 months ago
- Siglent SDS1x0xX-E FPGA bitstreams☆41Updated 4 months ago
- LiteX project for the ButterStick bootloader☆13Updated 2 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 6 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 5 months ago
- Experimental flows using nextpnr for Xilinx devices☆45Updated 2 weeks ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆98Updated last year
- An FPGA reverse engineering and documentation project☆44Updated last week
- Industry standard I/O for Amaranth HDL☆28Updated 7 months ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆14Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs☆108Updated 3 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆41Updated this week
- ☆45Updated 3 years ago